1. Field of the Invention
An aspect of the present invention relates to a semiconductor integrated device.
2. Description of the Related Art
A conventional level-shifting circuit has first and second p-channel metal oxide semiconductor (PMOS) transistors, each of which is connected to the drain of an associated one of first and second n-channel metal oxide semiconductor (NMOS) transistors as a load and has a gate cross-connected to the drain of the other PMOS transistor. In the conventional level-shifting circuit, as a voltage difference between before and after the level-shifting increases, an output signal is not completely inverted even when an input signal is inverted, and an operation is unstable.
Accordingly, although it is necessary to enhance drive capability by increasing gate lengths of the first and second NMOS transistors, it results increasing of the consumption current and the circuit area.
A semiconductor integrated device addressing these problems is known, which has a level-shifting circuit that adequately operates even if the ratio of a voltage before level-shifting to a voltage after the level-shifting is increased (see, e.g., JP-2002-076882-A).
The semiconductor integrated device disclosed in JP-2002-076882-A is provided with a level-shifting circuit that has an input node to which an input signal having a first amplitude is input and an output node from which an output signal having a second amplitude differing from the first amplitude is output, and that level-shifts the input signal having the first amplitude to the output signal having the second amplitude. This semiconductor integrated device is provided also with a current mirror circuit which charges the output node, and with a switch circuit which operates the current mirror circuit from when the input signal is inverted to when the output signal is inverted and which stops the current mirror circuit when the inversion has been finished.
However, since it takes time to stop an operation of the current mirror circuit in the semiconductor integrated device disclosed in JP-2002-076882-A, when the frequency of an input signal is increased, an output signal is not completely inverted, and the level-shifting circuit does not adequately operate.